The scaling of VLSI circuits is a constant effort. Smaller integrated circuits allow more devices to be formed in one semiconductor chip. Additionally, power consumption and performance are also improved. With circuits becoming smaller and faster, however, the distance between devices decreases. The gap-filling between neighboring devices thus suffers from problems. The gap-filling problem may be explained using FIGS. 1A through 1D. Referring to FIG. 1A, gate stacks 4 and 14 are formed close to each other. Gate spacers 6 and 16 are formed on sidewalls of gate stacks 4 and 14, respectively. Referring to FIG. 1B, gate spacers 6 and 16 are thinned, so that their thickness T1 as shown in FIG. 1A is reduced to thickness T1′ as in FIG. 1B. In FIG. 1C, contact etch stop layer (CESL) 8 is formed over gate stacks 4 and 14, wherein CESL 8 extends into gap 5 between gate stacks 4 and 14. Next, as shown in FIG. 1D, dielectric material 18 is formed to fill gap 5.
During the step shown in FIG. 1B, the thinning of gate spacers 6 and 16 causes the reduction of the aspect ratio of gap 5, wherein the aspect ratio of gap 5 may be defined as the ratio of height H to width W. Accordingly, in the structure shown in FIG. 1D, better gap-filling can be achieved. However, with the further reduction of the scale of integrated circuits, the aspect ratio of gap 5 continuously rises. Accordingly, even with the thinning of gate spacers 6 and 16, voids 19 may still form in dielectric material 18. Particularly, for gate-last approaches, hard masks are formed on gate stacks, causing the increase of height H of the gate stacks 4 and 14. This further causes the aspect ratio of gap 5 to be increased. Accordingly, a new method for forming MOS devices with improved gap-filling ability is needed.